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Principal/Lead Design Verification Engineer - UVM/SoC

15 - 18 yrs

Multiple Locations

SoCUVMDesign VerificationSystem Verilog+2

Posted 1 month ago

Neurealm - Principal/Lead DFT Engineer

15 - 18 yrs

Multiple Locations

SoCDFTASICATPGRTLStatic Timing Analysis+4+1

Posted 1 month ago

Synopsys - Staff/Principal Application Engineer - Formal Verification

4 - 15 yrs

Bangalore

SoCVerificationDesign VerificationRTL DesignSystem Verilog+3

Posted 1 month ago

VeriFast Technologies - IoT Solution Architect - Embedded Systems/AI

8 - 13 yrs

Ahmedabad

SoCIoTSolution DesignSolution ArchitectEmbedded CC++Firmware+5+2

Posted 1 month ago

VeriFast Technologies - Physical Design Engineer - ASIC/SoC

5 - 10 yrs

20-27 LPA

Ahmedabad

SoCPhysical DesignASICFloor PlanningSynthesisRTL Design+4+1

Posted 1 month ago

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Android Audio Software Engineer

3 - 5 yrs

Bangalore

Diversity Inclusive

SoCAndroid FrameworkHardware Abstraction LayerAudio HALALSADevice Driver+4+1

Posted 2 months ago

Modernize Chip Solutions - Design Verification Engineer - SerDes/SoC

4 - 5 yrs

Bangalore

SoCDesign VerificationSERDES+1

Posted 2 months ago

VeriFast Technologies - Lead Design Verification Engineer - System Verilog

10 - 15 yrs

Ahmedabad/Gujarat

SoCDesign VerificationUVMSystem VerilogCC+++4+1

Posted 2 months ago

Sandisk - Principal Software Engineer - Firmware Embedded System

9 - 14 yrs

Bangalore

SoCFirmwareC++CRTOSEmbedded System+4+1

Posted 2 months ago

Sandisk - ASIC Digital Engineer - SoC Validation

5 - 8 yrs

Bangalore

SoCASICSystem ValidationCEmbedded SystemSoC VerificationHardware Abstraction Layer+5+2

Posted 2 months ago

Western Digital - Staff VLSI Design Engineer

8 - 12 yrs

Bangalore

SoCVLSIVerificationUVMSystem VerilogRTLC+5+2

Posted 2 months ago

DFT Engineer

3 - 15 yrs

Bangalore

SoCDFTMBISTDesign Verification+2

Posted 2 months ago

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RTL Design Engineer

3 - 10 yrs

Chennai/Pune

SoCRTLRTL DesignARMFPGAStatic Timing Analysis+4+1

Posted 2 months ago

SignOff Semiconductors - Senior Physical Design Manager

12 - 20 yrs

Bangalore

SoCPhysical DesignSynthesisTiming Closure+2

Posted 1 month ago

Staff Engineer/Senior Staff Engineer - RTL/SoC

9 - 18 yrs

Bangalore/Chennai

SoCRTL DesignVerilogSystem VerilogSynthesisStatic Timing AnalysisRTL+5+2

Posted 1 month ago

DFT Engineer - SoC/ASIC

7 - 12 yrs

30-45 LPA

Bangalore

SoCDFTASICMBISTATPG+3

Posted 1 month ago

RARR Technologies - Android Developer Lead - C/C++ Programming

6 - 11 yrs

Coimbatore

SoCAndroid FrameworkAndroid AOSPHIDLCC+++4+1

Posted 1 month ago

BITSILICA - ASIC Verification Lead - Verification

5 - 8 yrs

Bangalore

SoCASICVerificationUVMPythonSystem Verilog+4+1

Posted 1 month ago

Bitsilica - Senior Staff Engineer - DFT

10 - 15 yrs

Bangalore/Karnataka

SoCDFTATPGMBISTVerification+3

Posted 1 month ago

BITSILICA - Design Verification Manager - SoC/ASIC

6 - 12 yrs

Bangalore

SoCVerificationDesign VerificationASICSystem Verilog+3

Posted 1 month ago

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